1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device wherein grooved separating regions are formed between the respective memory cells, with portions of information electric charge storing capacitances of memory cells formed on the side surfaces of the grooved separating regions.
2. Description of the Prior Art
FIGS. 1A and 1B show a memory cell of a dynamic type semiconductor memory device of a large scale integration proposed in Lecture No. FAM17.4 in International Solid State Circuit Conference in 1985 (ISSCC85), wherein FIG. 1B shows a sectional view taken along the line X-X' in FIG. 1A. Referring to the figures, on a P type substrate 1 are layered an N.sup.+ type diffusion layer 5, a field oxide film 2, a first polycrystalline silicon layer 3, a second polycrystalline silicon layer 7, a first aluminum wiring layer 6, a second aluminum wiring layer 8, an interlayer insulating film 9 and the like. The first aluminum wiring layer 6 is to become bit lines and is in electrical contact with the N.sup.+ type diffusion layer 5 through a contact hole 10. The second polycrystalline silicon layer 7 is to become word lines and is short circuited to the second aluminum wiring layer 8 at predetermined intervals, thereby to decrease the resistance.
It is to be noted that grooved separating regions are formed around the memory cell MC for the purpose of separating the respective memory cells. Use is made of the side surfaces of the grooved separating regions so that an information electric charge storing capacitance Cp may be formed with the first polycrystalline silicon layer 3, the capacitor insulating film 4 (a portion of the field oxide film 2) and N.sup.+ type diffusion layer. An information electric charge storing capacitance C.sub.F is also formed in the same structure on the flat portion of the memory cell MC.
The features of the above described conventional structure are that when the chip area is reduced, by decreasing the area of a flat portion having information electric charge storing capacitances C.sub.F formed through active use of the grooved separating portions of the outer peripheral portions of the memory cells MC as information electric charge storing capacitances a sufficiently broad operation margin with sufficient electric charge storing capacitances capable of maintaining ample stored information electric charges for minor carriers injected through radiation such as .alpha. particles.
Meanwhile, as shown in FIG. 1A, the longer the length of the memory cell MC, the smaller the depth of the grooves required for providing the same amount of the capacitances C.sub.F.
Incidentally described, in situations when the structure of the above described conventional example wherein information electric charge storing regions are formed on grooved separating regions is applied to a folded type bit line structure as shown in Patent Laying-Open No. 74535/1976, the cross sectional structure taken along the line Y-Y' in FIG. 1A becomes as shown in FIG. 2. A semiconductor memory device with such cross sectional structure has the following problems: following.
(1) Since the first polycrystalline silicon layer 3 is patterned in the grooved separating regions is patterning is difficult. The reason is that since the depth of the first polycrystalline silicon layer 3 is changeable in the grooved separating regions, focusing for the purpose of patterning becomes difficult and setting of the etching condition is also difficult.
(2) Since the grooved separating regions are formed on both sides of the channel region of the gate transistor GT which is controlled by the second polycrystalline silicon layer 7 becoming the word line, control of a leak current at the edge (the portion shown by A in FIG. 2) of the channel region of the gate transistor GT is difficult.
(3) Since the second polycrystalline silicon layer 7 becoming the word line extends across the grooved separating regions, an offset of the word line is increased and the patterning becomes difficult while consideration is required in burying grooved separating regions within the insulating film.